Semiconductor apparatus including power semiconductor device constructed by using wide band gap semiconductor

ABSTRACT

A semiconductor apparatus includes a semiconductor chip  61  including a power semiconductor device using a wide band gap semiconductor, base materials  62  and  63 , first and second intermediate members  65  and  68   a , a heat conducting member  66 , a radiation fin  67 , and an encapsulating material  68  for encapsulating the semiconductor chip  61 , the first and second intermediate member  65  and  68   a  and the heat conducting member  66 . The tips of the base materials  62  and  63  work respectively as external connection terminals  62   a  and  63   a . The second intermediate member  68   a  is made of a material with lower heat conductivity than the first intermediate member  65 , and a contact area with the semiconductor chip  61  is larger in the second intermediate member  68   a  than in the first intermediate member.

TECHNICAL FIELD

The present invention relates to a MISFET formed by utilizing a compoundsemiconductor layer, and more particularly, it relates to a MISFETsuitably used for a high breakdown voltage and a large current.

BACKGROUND ART

In a power module composed of a plurality of semiconductor chipsincluding a power device, it is conventionally a significant problem todiffuse heat of a semiconductor device generated through power loss ofthe power device (for example, see Document 1 (Power ElectronicsHandbook (R & D Planning), edited by Koji Imai (p. 602)). Therefore, aconventional semiconductor apparatus is designed, for cooling a powerdevice and keeping its temperature below the safety operatingtemperature, to place the power device in contact with the package basematerial so that heat generated in the power device can be releasedthrough a package base material through heat conduction. Accordingly, inthe case where a power module is constructed by using a plurality ofsemiconductor chips, it is necessary to make every semiconductor devicein contact with a package base material.

FIG. 11 is a cross-sectional view of a conventional semiconductor powermodule composed of three Si power devices. As shown in FIG. 11, theconventional semiconductor power module includes a base material 101provided with a fin 101 a on its back face for releasing heat, Si chips102, 103 and 104 corresponding to the three Si power devices secured onthe upper face of the base material 101 through soldering, and bondingwires 105 for electrically connecting the Si chips 102, 103 and 104 toone another. Owing to this structure, heat generated in the Si chips102, 103 and 104 can be efficiently diffused to the base material 101through the heat conduction, and therefore, the temperatures of the Sichips 102, 103 and 104 corresponding to the power devices can besuppressed to 150° C. or less, that is, their temperature assurancerange.

PROBLEMS TO BE SOLVED BY THE INVENTION

In the conventional semiconductor power module, however, in order tomount the plural Si chips 102, 103 and 104 included in the semiconductorpower module respectively on the base material 101, the base material101 needs to have an area larger than at least the total areas of the Sichips 102, 103 and 104. As a result, the package area of thesemiconductor power module used for dealing with a comparatively largecurrent is unavoidably large.

In particular, in the case where the Si chip, that is, a conventionalpower device, is a MOSFET, an IGBT, a diode or the like, the powermodule is designed, in consideration of the thermal conductivity of Siof approximately 1.5 W/cmK, so that heat generated by a current flowingto the Si chip during the operation can be efficiently released and thatthe temperature of a portion having the highest current density in theSi chip cannot exceed 150° C. The semiconductor power device included inthe Si chip cannot control current when the temperature exceeds 150° C.because thermal runaway is caused therein to put the device in ashort-circuited state at that temperature. For example, when the currentdensity within the semiconductor power device is 10 A/cm² or more duringits operation, it is necessary to provide means for releasing heatgenerated within the semiconductor power device. In particular, when thecurrent density within the semiconductor power device is 50 A/cm² ormore, the heat generated within the semiconductor power device isremarkably large, and hence, it is necessary to provide an adequatemeasure to design for releasing the heat.

Since the heat release is significant in the design of a semiconductorpower module as described above, a Si chip corresponding to a powerdevice is designed to be definitely in contact with a base materialworking as a heat releasing path and is directly connected to the basematerial through soldering or the like by a method designated as diebonding. As a result, the area of a semiconductor apparatus isunavoidably large.

Also, in order to electrically connect a plurality of semiconductordevices arranged on the base material with a large area, long bondingwires are necessary. Therefore, there arises another problem that theelectric resistance of the long wires further increases the power lossderived from the electric resistance of the semiconductor apparatus.

Furthermore, in the case where the base material is a lead or a die pad,its end portion corresponds to an external connection terminal to beconnected, through soldering or the like, to a mother substrate such asa print wiring board. When the temperature of the external connectionterminal becomes too high as a result of a large amount of heat releasedto the base material, it is apprehended that the reliability of theconnection to the mother substrate is degraded because a bonding metalsuch as the solder is melted or the connection is weakened.

DISCLOSURE OF THE INVENTION

An object of the invention is providing a power semiconductor apparatuscapable of allowing a large current to efficiently flow and using a wideband gap semiconductor device with high reliability in connection to amother substrate.

The first semiconductor apparatus of this invention includes asemiconductor chip including a power semiconductor device using a wideband gap semiconductor; an electrically conductive base materialconnected to a part of a face of the semiconductor chip and having a tipworking as an external connection terminal; a heat conducting member incontact with a part of the face of the semiconductor chip; and anencapsulating material for encapsulating them.

Accordingly, most of heat generated from the semiconductor chip, thatis, a source of large heat, is transmitted through the heat conductingmember to be released outside the semiconductor apparatus, and theamount of heat transmitted to the external connection terminal is small.Therefore, connection reliability at the connection between a mothersubstrate and the external connection terminal is never degraded due totemperature increase, and hence, high reliability can be kept whilekeeping the power semiconductor device at an appropriately hightemperature for attaining high efficiency.

When the power semiconductor device has a region where a current passesat a current density of 50 A/cm² or more, application of the structureof this invention is significant.

When the encapsulating material is made of a resin or glass and the heatconducting member is exposed from the encapsulating material, thefunction to release the heat is further increased.

When the semiconductor apparatus further includes a radiation fin thatis in contact with the heat conducting member and is extruded outsidethe encapsulating material, the heat releasing property can be furtherimproved.

The semiconductor apparatus may further include a film for covering theencapsulating material. In this case, the semiconductor apparatuspreferably further includes a radiation fin opposing the heat conductingmember with the film sandwiched therebetween.

When a first intermediate member made of an electrically conductivematerial and a second intermediate member made of a material havinglower heat conductivity than the first intermediate member are providedbetween the base material and the semiconductor chip, the transmittanceof the heat to the base material can be appropriately adjusted.

When a contact area between the semiconductor chip and the base materialis smaller than a half of an area of the semiconductor chip, thetransmittance of the heat to the base material can be effectivelysuppressed.

When the power semiconductor device is a vertical element and thesemiconductor apparatus further includes another semiconductor chip thatis stacked on the semiconductor chip and a part of which is connected tothe base material, a semiconductor module can be constructed.

Also in the case where the external connection terminal of the basematerial is constructed to be mounted on a print wiring board, theconnection reliability can be kept by applying the present invention.

When the wide band gap semiconductor is SiC, the semiconductor apparatuscan function as a power device with a particularly large output.

The second semiconductor apparatus of this invention includes asemiconductor chip including a power semiconductor device using a wideband gap semiconductor; an electrically conductive base materialconnected to a part of a face of the semiconductor chip; a heatconducting member in contact with a part of the face of thesemiconductor chip; a vessel in contact with the heat conducting memberand encapsulating the semiconductor chip, the base material and the heatconducting member; and an external connection terminal electricallyconnected to the base material and extruded from the vessel.

Accordingly, most of heat generated from the semiconductor chip, thatis, a source of large heat, is transmitted through the heat conductingmember and the vessel to be released to the outside the semiconductorapparatus, and the amount of heat transmitted to the external connectionterminal is small. Therefore, connection reliability at the connectionbetween a mother substrate and the external connection terminal is neverdegraded due to temperature increase, and hence, high reliability can bekept while keeping the power semiconductor device at an appropriatelyhigh temperature for attaining high efficiency.

When a region around the semiconductor chip, the base material and theheat conducting member within the vessel is filled with glass, a resin,an inert gas or a gas reduced in pressure, the environment within thevessel can be kept more satisfactorily and hence high reliability can beexhibited.

The second semiconductor apparatus preferably further includes aradiation fin opposing the heat conducting member with a part of thevessel sandwiched therebetween.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross-sectional view for showing the structure of asemiconductor apparatus (power module) according to Embodiment 1 of theinvention.

FIGS. 2A and 2B are respectively a cross-sectional view and an electriccircuit diagram of a semiconductor apparatus according to Example 1 ofEmbodiment 1.

FIGS. 3A and 3B are respectively a cross-sectional view and an electriccircuit diagram of a semiconductor apparatus according to Example 2 ofEmbodiment 1.

FIGS. 4A and 4B are respectively a cross-sectional view and an electriccircuit diagram of a semiconductor apparatus according to Example 3 ofEmbodiment 1.

FIGS. 5A and 5B are cross-sectional views for showing two exemplifiedstructures of a semiconductor apparatus according to Embodiment 2 of theinvention.

FIG. 6 is a cross-sectional view of a semiconductor apparatus accordingto Example 1 of Embodiment 2.

FIGS. 7A through 7C are cross-sectional views for showing fabricationprocedures for the semiconductor apparatus of Example 1 of Embodiment 2.

FIG. 8 is a cross-sectional view for showing exemplified mounting of apower transistor TR1 on a print wiring board.

FIG. 9 is a cross-sectional view of a semiconductor apparatus accordingto Example 2 of Embodiment 2.

FIG. 10 is a cross-sectional view of a semiconductor apparatus accordingto Example 3 of Embodiment 2.

FIG. 11 is a cross-sectional view of a conventional semiconductorapparatus.

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1

FIG. 1 is a cross-sectional view for showing the structure of asemiconductor apparatus (power module) according to Embodiment 1 of theinvention.

The semiconductor apparatus (semiconductor power module) according toEmbodiment 1 of the invention includes, as shown in FIG. 1, a basematerial 11 made of a metal material such as Cu and first through thirdsemiconductor chips 12, 13 and 15 (such as a transistor, a diode and anIGBT) different from one another in the size or function and stacked onthe base material 11. As characteristics of this semiconductor powermodule, the semiconductor chips 12, 13 and 15 are stacked with theelectrode of at least one semiconductor chip out of the semiconductorchips 12, 13 and 15 connected to the electrode or an active region ofanother semiconductor chip, and at least one semiconductor chip out ofthe plural semiconductor chips 12, 13 and 15 includes a semiconductorpower device constructed by using a wide band gap semiconductor.

Differently from a semiconductor power module including a conventionalSi power device, the semiconductor power module of this embodimentincludes a plurality of semiconductor chips at least one of whichincludes a semiconductor power device using a wide band gapsemiconductor, and employs the structure where the semiconductor chipsare stacked. Therefore, compactness and area reduction that cannot beattained by the conventional semiconductor power module can be realized.

The “wide band gap semiconductor” herein means a semiconductor with aband gap, that is, an energy difference between the lower end of theconduction band and the upper end of the valence band, of 2.0 eV ormore. Examples of such a wide band gap semiconductor are silicon carbide(SiC), a nitride of a group III element such as GaN or AlN, diamond andthe like.

In the semiconductor power module of this invention, any of knownsemiconductor chips can be unboundedly used, and examples of thesemiconductor chip are a Schottky diode, a pn diode, a MISFET, a MESFET,a J-FET, a thyrister and the like. Also, one of the plural semiconductorchips may be a passive element such as a capacitive element, aninductive element or a resistance element.

Methods for connecting the semiconductor chips to one another are directbonding utilizing interdiffusion of metals, bonding through soldering,connection using a bump, connection utilizing an electrically conductiveadhesive and the like, any of which may be employed.

Furthermore, any of known packages can be unboundedly used, and examplesof the package are a resin-encapsulation package, a ceramic package, ametal package and a glass package. In using any of the packages, a basematerial made of a metal with comparatively high heat conductivity (suchas Cu) is generally used.

In general, the heat conductivity of a wide band gap semiconductor has avalue several times as large as that of Si, and silicon carbide (SiC)has heat conductivity of 4.9 W/cmK and diamond has heat conductivity of20 W/cmK. Owing to such high heat conductivity, in the semiconductorpower module including a semiconductor power device using a wide bandgap semiconductor, the efficiency in releasing heat generated in thesemiconductor power device is comparatively high, and therefore, thetemperature increase in a portion with a high current density in thesemiconductor power device can be suppressed to be comparatively small.Specifically, in the case where the semiconductor chips 12, 13 and 15are stacked as shown in FIG. 1, even when the semiconductor chips 12, 13and 15 are provided at a high density in the semiconductor power modulewith a small area, the heat generated in the semiconductor power devicecan be efficiently released to the base material 11. Therefore, aportion with a high current density in the semiconductor power device(such as a source region of a power transistor) can be kept at acomparatively low temperature.

Also, in comparison between MISFETs having equivalent breakdown voltagesof 1 kV, the semiconductor power device using the wide band gapsemiconductor has power loss smaller by one or more figures than a Sipower device. In comparison between a Si IGBT and a MISFET using a wideband gap semiconductor, the semiconductor power device using the wideband gap semiconductor has power loss a half or less of that of the Sipower device. Owing to the small power loss property of thesemiconductor power device using the wide band gap semiconductor, theheat itself generated within the semiconductor power device is alsosmall in the semiconductor power module of this invention, andtherefore, as compared with a semiconductor power module using aconventional Si power device, the internal temperature increase can bemore advantageously suppressed.

Furthermore, since a MISFET using a wide band gap semiconductor canattain a high breakdown voltage and small power loss property superiorto an IGBT using Si, the high speed operation property of the MISFET canbe usefully used for controlling a signal of a high voltage/largecurrent. In other words, switching loss caused when the operation speedof a semiconductor power device is low can be reduced.

In particular, in the case where a current with a current density of 50A/cm² or more flows to at least one of the plural semiconductor chips inthe semiconductor power module, the effect of this invention isremarkably exhibited. This is for the following reason: In an operationwhere a current density of 50 A/cm² or more occurs in the semiconductorchip, the heat generated in accordance with the power loss is increasedin a Si power device (such as a MISFET), and therefore, it is difficultto continue the operation within the bound of the temperature of 150° C.or less necessary for keeping a normal operation of the Si power device.On the contrary, in the semiconductor power module of this invention,the amount of generated heat is suppressed even when the current densityexceeds 50 A/cm², and hence, the operation can be satisfactorilyperformed.

Furthermore, even when the temperature of the semiconductor power deviceusing the wide band gap semiconductor (such as SiC) is increased to be200° C. or more (or further to be 400° C. or more), the semiconductorpower module can be satisfactorily operated. Rather, the electricresistance of the semiconductor power device is reduced as thetemperature increases, and therefore, the semiconductor power module isfound to be able to be more efficiently operated owing to the reducedelectric resistance in the case where it is operated with a currentdensity of 50 A/cm² or more and is kept at a high temperature than inthe case where it is kept at a low temperature.

In other words, in the semiconductor power module of this invention,since a plurality of semiconductor chips including at least onesemiconductor power device using a wide band gap semiconductor arestacked, the operation efficiency is rather increased when the internaltemperature is increased as compared with a conventional semiconductorpower module in which semiconductor chips are not stacked as shown inFIG. 11.

Furthermore, as shown in FIG. 1, the second semiconductor chip 13stacked on the first semiconductor chip 12 is preferably larger than thefirst semiconductor chip 12 in contact with the base material 11 of thesemiconductor apparatus. This is because, when the first semiconductorchip 12 corresponding to a heat releasing path to the base material 11is smaller, the amount of heat released from the second semiconductorchip 13 to the base material 11 is small, and hence, the secondsemiconductor chip 13 is operated at a higher temperature, resulting inattaining the aforementioned effect to improve the operation efficiencydue to the low-loss operation.

Moreover, the plural semiconductor chips 12, 13 and 15 are preferablystacked in three or more layers. This is because the heat generated in asemiconductor chip disposed on the uppermost layer of three or morestacked layers is less released as described above, and therefore, theaforementioned effect to improve the operation efficiency owing to thetemperature increase of the semiconductor chip can be more remarkablyattained.

Also, the semiconductor chip using the wide band gap semiconductor ispreferably a vertical element whose main current flows between the upperface and the lower face of the substrate (such as a vertical MISFET, avertical diode (a Schottky diode, a pn diode or a pin diode) or avertical IGBT). This is because a vertical element is particularlysuitable to the stacked structure because the current flows between theupper face and the lower face of the substrate.

Furthermore, in the semiconductor power module, the wide band gapsemiconductor is preferably silicon carbide (SiC). As semiconductormaterials for providing a semiconductor chip capable of operating as apower device even at a high temperature, silicon carbide (SiC), anitride of a group III element such as GaN or AlN, and diamond aresuitable as described above, and it has been confirmed that SiC (a4H—SiC substrate in particular) is particularly good at the low-lossproperty, stability, reliability and the like. This is because waferswith a low defect density are supplied, and hence, there minimallyarises a problem of dielectric breakdown or the like derived from adefect caused in the crystal.

Example 1

FIGS. 2A and 2B are respectively a cross-sectional view and an electriccircuit diagram of a semiconductor apparatus according to Example 1 ofEmbodiment 1.

As shown in FIG. 2B, the semiconductor apparatus (semiconductor powermodule) of this example functions as a boosting type DC-DC converter forboosting an input DC signal (input DC) and outputting an output DCsignal (output DC). The semiconductor power module includes an inductiveelement IND1, a power transistor TR1, that is, a vertical MISFET, aSchottky diode D1 and a capacitive element CA1.

As shown in FIG. 2A, the Schottky diode D1 includes an N-type driftlayer 21 (active region) occupying most of a SiC substrate made of awide band gap semiconductor, and a Schottky electrode 22 made of Ni inSchottky contact with the N-type drift layer 21. The N-type drift layer21 is connected to a base material 23 made of a metal such as Cu, andthe base material 23 is connected to an output terminal for outputtingan output voltage Vout.

On the other hand, the power transistor TR1 includes an n-type driftlayer 31 (active region) occupying most of a SiC substrate made of awide band gap semiconductor; a P-type base layer 32 formed in the N-typedrift layer 31 by doping it with a P-type impurity; an N⁺-type sourcelayer 33 formed in the P-type base layer 32 by doping it with a highconcentration N-type impurity; a gate insulating film 35 of a siliconoxide film formed in a surface portion of the SiC substrate over theP-type base layer 32, the N-type drift layer 31 and the N⁺-type sourcelayers 33 sandwiching the P-type base layer 32; a gate electrode 36 madeof a metal such as Al or polysilicon and provided on the gate insulatingfilm 35; a source electrode 37 formed in a surface portion of the SiCsubstrate over the N⁺-type source layers 33 sandwiching the P-type baselayer 32; an interlayer insulating film 38 of a silicon oxide filmprovided on the SiC substrate; a gate interconnect/plug 40 made of ametal such as Al and penetrating the interlayer insulating film 38 so asto be connected to the gate electrode 36; a leading electrode 42 of thegate interconnect/plug 40; and a source interconnect/plug 41 made of ametal such as Al and penetrating the interlayer insulating film 38 to beconnected to every source electrode 37. A portion of the sourceinterconnect/plug 41 positioned on the upper face of the interlayerinsulating film 38 is provided in the shape of a plate, this portion isconnected to a base material 43 made of a metal such as Cu, and the basematerial 43 is connected to the ground. Also, a back electrode 39 madeof a metal such as Ni or Ni silicide alloy is provided on the lower faceof the N-type drift layer 31, and the back electrode 39 is connected tothe Schottky electrode 22 of the Schottky diode D1.

Furthermore, the leading electrode 42 is connected to an interconnect52, and the interconnect 52 is connected to a gate voltage controldriver. The back electrode 39 is connected to an interconnect 51, andthe interconnect 51 is connected to an input terminal for receiving aninput voltage Vin through the inductive element IND1 corresponding to achip inductor. Also, the capacitive element CA1 corresponding to a chipcapacitor is sandwiched between the base material 23 and the basematerial 43.

Next, fabrication procedures for the semiconductor power module of thisexample will be described.

First, the N-type drift layer 21 of the Schottky diode D1, that is, acomparatively small semiconductor power device, is bonded on the upperface of the base material 23 by, for example, soldering. At this point,bonding is performed by using AuSn solder or SnAgCu solder at 300° C.

Next, the power transistor TR1, that is, a comparatively largesemiconductor chip, is bonded on the upper face of the Schottkyelectrode 22 of the Schottky diode D1. The bonding between the Schottkydiode D1 and the power transistor TR1 may be performed by soldering, butin this example, the Schottky electrode 22 of the Schottky diode D1 andthe back electrode 39 of the power transistor TR1 are pushed againsteach other so as to bond them by utilizing interdiffusion of the metal.In this bonding, weighting of 0.1 through 1 kg/cm² and ultrasonic of 60through 120 kHz are applied.

Furthermore, the base material 43 is mounted on the upper face of thesource interconnect/plug 41 of the power transistor TR1 by using solderfor bonding them to each other. In this case, a gold plate bump may beprovided on the upper face of the source interconnect/plug 41 forultrasonic bonding to the base material 43. The interconnects 51 and 52are respectively connected to the back electrode 39 and the leadingelectrode 42 of the power transistor TR1, the inductive element IND1corresponding to the chip inductor is connected to the interconnect 51and the capacitive element CA1 corresponding to the chip capacitor isconnected between the base materials 23 and 43. Thereafter, the Schottkydiode D1, the power transistor TR1, the capacitive element CA1, theinductive element IND1, the capacitive element CA1 and the interconnects51 and 52 are assembled as one package by resin-encapsulation. Themethod for the resin-encapsulation is not shown in the drawing but anyof various known resin-encapsulation techniques can be employed. At thispoint, the inductive element IND1 corresponding to the chip inductor andthe capacitive element CA1 corresponding to the chip capacitor may beexternally provided without being integrated within the package.

In the conventional semiconductor power module, the semiconductor chips103 and 104 are both connected to the upper face of the base material101. In the semiconductor power module of this example, however, thepower transistor TR1 is stacked on the Schottky diode D1 correspondingto a semiconductor chip, and therefore, the area occupied by thesemiconductor power module is reduced.

Also, a power module having the same structure as the semiconductorpower module of this example is constructed by using a pn diode and apower transistor using Si, so as to be compared with the power module ofthis example. Assuming that the power transistor TR1 is a chip 3 mmsquare, the junction temperature exceeds 150° C. with rating of acurrent of 5 A in the conventional semiconductor power module using theSi chip, but in the semiconductor power module of this example, acurrent of 10 A or more can be allowed to flow, and it is confirmed thatthe semiconductor power module is stably operated even when a currentflows to the N⁺-type source region 33 of the power transistor TR1 at acurrent density of 50 A/cm² or more. At this point, the junctiontemperature of the power transistor TR1 and the Schottky diode D1 ofthis example is kept at 150° C. or less.

Furthermore, it is confirmed that the semiconductor power module of thisexample is stably operated even when a current of 20 A is allowed toflow. In this case, as compared with the case where a current of 10 A isallowed to flow, although the junction temperature of the Schottky diodeD1 and the power transistor TR1 is increased beyond 150° C., it is alsoconfirmed that the loss factor is reduced by increasing the currentbecause the electric resistance of the power transistor TR1 is reduced.

Example 2

FIGS. 3A and 3B are respectively a cross-sectional view and an electriccircuit diagram of a semiconductor apparatus according to Example 2 ofEmbodiment 1.

As shown in FIG. 3B, the semiconductor apparatus (semiconductor powermodule) of this example functions as a bucking DC-DC converter forbucking an input DC signal (input DC) and outputting an output DC signal(output DC). The semiconductor power module includes an inductiveelement IND1, a power transistor TR1, that is, a vertical MISFET, aSchottky diode D1 and a capacitive element CA1.

As shown in FIG. 3A, the Schottky diode D1 has the same structure as theSchottky diode D1 of Example 1. A Schottky electrode 22 is connected toa base material 23 made of Cu and the base material 23 is connected toan output terminal through the capacitive element CA1.

The power transistor TR1 also has the same structure as the powertransistor TR1 of Example 1. A portion of a source interconnect/plug 41positioned on the upper face of an interlayer insulating film 38 isbonded to an N-type drift layer 21 of the Schottky diode D1. Also, aback electrode 39 is bonded to a base material 43 made of a metal suchas Cu, and the base material 43 is connected to an input terminal forreceiving an input voltage Vin.

Furthermore, a leading electrode 42 is connected to an interconnect 52,and the interconnect 52 is connected to a gate voltage control driver.Also, a portion of the source interconnect/plug 41 positioned on theupper face of the interlayer insulating film 38 is connected to aninterconnect 54, and the interconnect 54 is connected to an outputterminal for outputting an output voltage Vout through the inductiveelement IND1 corresponding to a chip inductor.

Fabrication procedures for the semiconductor power module of thisexample are basically the same as those described in Example 1 and hencethe description is omitted.

Example 3

FIGS. 4A and 4B are respectively a cross-sectional view and an electriccircuit diagram of a semiconductor apparatus according to Example 3 ofEmbodiment 1.

As shown in FIG. 4B, the semiconductor apparatus (semiconductor powermodule) of this example functions as an inverting DC-DC converter forinverting an input DC signal with a positive voltage (input DC) andoutputting an output DC signal with a negative voltage (output DC). Thesemiconductor power module includes an inductive element IND1, a powertransistor TR1, that is, a vertical MISFET, a Schottky diode D1 and acapacitive element CA1.

As shown in FIG. 4A, the Schottky diode D1 has the same structure as theSchottky diode D1 of Example 1. A Schottky electrode 22 is connected toa base material 23 made of a metal such as Cu, and one end of the basematerial 23 is connected to an output terminal with the other endthereof connected to the ground through the capacitive element CA1.

The power transistor TR1 also has the same structure as the powertransistor TR1 of Example 1. A portion of a source interconnect/plug 41positioned on the upper face of an interlayer insulating film 38 isbonded to an N-type drift layer 21 of the Schottky diode D1. Also, aback electrode 39 is connected to a base material 43 made of a metalsuch as Cu, and the base material 43 is connected to an input terminalfor receiving a positive input voltage Vin.

Furthermore, a leading electrode 42 is connected to an interconnect 52,and the interconnect 52 is connected to a gate voltage control driver.Also, the portion of the source interconnect/plug 41 positioned on theupper face of the interlayer insulating film 38 is connected to aninterconnect 55, and the interconnect 55 is connected to the groundthrough the inductive element IND1 corresponding to a chip inductor.

Fabrication procedures for the semiconductor power module of thisexample are basically the same as those described in Example 1 and hencethe description is omitted.

Embodiment 2

FIGS. 5A and 5B are cross-sectional views for showing two exemplifiedstructures of a semiconductor apparatus according to Embodiment 2 of theinvention.

In the first exemplified structure, as shown in FIG. 5A, thesemiconductor apparatus according to Embodiment 2 of the inventionincludes a semiconductor chip 61 containing a power semiconductor deviceusing a wide band gap semiconductor; a base material 62 corresponding toa die pad made of an electrically conductive metal material such as Cu;a base material 63 corresponding to a lead made of a metal material suchCu and connected to a pad electrode (not shown) of the semiconductorchip 61; a first intermediate member 65 and a second intermediate member68 a disposed between the semiconductor chip 61 and the base material 62and in contact with a part of the semiconductor chip 61; a heatconducting member 66 in contact with the semiconductor chip 61 and madeof a material with high heat conductivity (such as a metal or ceramic);a radiation fin 67 provided on the heat conducting member 66; and anencapsulating material 68 for encapsulating the semiconductor chip 61,the first and second intermediate members 65 and 68 a and the heatconducting member 66. Respective tips of the base materials 62 and 63are extruded outside the encapsulating material 63, so as to work asexternal connection terminals 62 a and 63 a for use in mounting thesemiconductor apparatus on a print wiring board or the like.

In this embodiment, the material of the semiconductor chip 61 includingthe power semiconductor device using the wide gap semiconductor, thetypes of transistor and diode, and the like are the same as thosedescribed in Embodiment 1.

The second intermediate member 68 a is made of a material with lowerheat conductivity than the first intermediate member 65, and the contactarea with the semiconductor chip 61 is larger in the second intermediatemember 68 a than in the first intermediate member. For example, thefirst intermediate member 65 is made of copper with heat conductivity of4 (W/cm·deg) and the second intermediate member 68 a is made of amaterial with heat conductivity lower than 0.1 (W/cm·deg). In theexemplified structure shown in FIG. 5A, the second intermediate member68 a is a part of the encapsulating material 68. The heat conductingmember 66 is made of, for example, alumina (ceramic) with heatconductivity of 0.26 (W/cm·deg). The radiation fin 67 may be made of thesame material as the heat conducting member 66 or made of a metal suchas copper alloy. Alternatively, the radiation fin 67 may be a coolingmedium with large heat capacity.

Also, in the second exemplified structure, as shown in FIG. 5B, heatconducting members 66 in contact with respective faces of thesemiconductor chip 61 are provided. A radiation fin 67 is provided onthe face of each heat conducting member 66.

In the case where, for example, the power semiconductor device includedin the semiconductor chip 61 is a three-terminal type element (such as aMISFET) in either of the first and second exemplified structures asshown with broken lines in FIGS. 5A and 5B, it is necessary to provide abase material 64 corresponding to another lead connected to an electrodeof the semiconductor chip 61.

As a characteristic of the semiconductor apparatus of this embodiment,the heat conducting member 66 in contact with the semiconductor chip 61corresponding to the power device is provided so as to be exposed fromthe encapsulating material 68. Also, the base member 62 is connected tomerely a part of the semiconductor chip 61 through the firstintermediate member 65 and is not in contact with the whole face of thesemiconductor chip 61 differently from the conventional semiconductorpower module.

According to this embodiment, since the heat conducting member 66 incontact with the semiconductor chip 61 is provided so as to be exposedfrom the encapsulating material 68, heat generated within thesemiconductor chip 61 including the power semiconductor device isreleased through the heat conducting member 66, and the temperatures ofthe external connection terminals 62 a and 63 a are prevented from beingexcessively increased by the heat of the semiconductor chip 61, and inaddition, the semiconductor chip 61 can be kept at an appropriately hightemperature and in a state where high operation efficiency is attained.Accordingly, the connection between the external connection terminals 62a and 63 a and a mother substrate such as a print wiring board can beimproved. Also, compactness and area reduction can be realized owing tothe improvement of the heat releasing property.

In particular, since the base material 62 is connected not to the wholeface of the semiconductor chip 61 but to an area of ½ or less of theupper or lower face directly or with the conducting member sandwichedtherebetween, the temperature increase of the external connectionterminal 62 a corresponding to the tip of the base member 62 can beadvantageously more effectively suppressed.

Also when a mold resin with high heat resistance is used as theencapsulating material without providing the heat conducting member 66and the radiation fin 67, the excessive temperature increase of theexternal connection terminals 62 a and 63 a can be suppressed whileappropriately keeping the temperature of the semiconductor chip 61 forkeeping the high operation efficiency.

Alternatively, an encapsulating glass may be used as the encapsulatingmaterial instead of the encapsulating resin, and a film covering theencapsulating resin or encapsulating glass may be provided. In thiscase, the radiation fin is provided in a position opposing the heatconducting member with the encapsulating resin or encapsulating glasssandwiched therebetween.

Also, a chip including a semiconductor device such as a diode may beprovided between the heat conducting member 66 and the semiconductorchip 61, or a chip including a semiconductor device such as a diode maybe provided instead of the second intermediate member 68 a. In thiscase, a power module is obtained as in Embodiment 1.

In the semiconductor apparatus of this embodiment, any of knownsemiconductor chips can be unboundedly used, and for example, asemiconductor chip mounting a Schottky diode, a pn diode, a MISFET, aMESFET, a J-FET, a thyrister or the like may be used.

Methods for connecting the pad electrode of the semiconductor chip andthe base material to each other are direct bonding utilizinginterdiffusion of metals, bonding through soldering, connection using abump, connection utilizing an electrically conductive adhesive and thelike, any of which may be employed.

Furthermore, any of known packages can be unboundedly used, and examplesof the package are a resin-encapsulation package, a ceramic package, ametal package and a glass package. In using any of the packages, a basematerial made of a metal with comparatively high heat conductivity (suchas Cu) is generally used.

Also, in comparison between MISFETs having equivalent breakdown voltagesof 1 kV, the semiconductor power device using the wide band gapsemiconductor has power loss smaller by one or more figures than a Sipower device. In comparison between a Si IGBT and a MISFET using a wideband gap semiconductor, the semiconductor power device using the wideband gap semiconductor has power loss a half or less of that of the Sipower device. Owing to the small power loss property of thesemiconductor power device using the wide band gap semiconductor, theheat itself generated within the semiconductor power device is alsosmall in the semiconductor power device of this invention, andtherefore, as compared with a semiconductor power device using aconventional Si power device, the internal temperature increase can bemore advantageously suppressed.

Furthermore, since a MISFET using a wide band gap semiconductor canattain a high breakdown voltage and small power loss property superiorto an IGBT using Si, the high speed operation property of the MISFET canbe usefully used for controlling a signal of a high voltage/largecurrent. In other words, switching loss caused when the operation speedof a semiconductor power device is low can be reduced.

In particular, in the case where a current with a current density of 50A/cm² or more flows to at least one of a plurality of semiconductordevices in the semiconductor power module, the effect of this inventionis remarkably exhibited. This is for the following reason: In anoperation where a current density of 50 A/cm² or more occurs in thesemiconductor device, the heat generated in accordance with the powerloss is increased in a Si power device (such as a MISFET), andtherefore, it is difficult to continue the operation within the bound ofthe temperature of 150° C. or less necessary for keeping a normaloperation of the Si power device. On the contrary, in the semiconductorpower device of this invention, the amount of generated heat issuppressed even when the current density exceeds 50 A/cm², and hence,the operation can be satisfactorily performed.

Furthermore, even when the temperature of the semiconductor power deviceusing the wide band gap semiconductor (such as SiC) is increased to be200° C. or more (or further to be 400° C. or more), the semiconductorpower module can be satisfactorily operated. Rather, the electricresistance of the semiconductor power device is reduced as thetemperature increases, and therefore, the semiconductor power module isfound to be able to be more efficiently operated owing to the reducedelectric resistance in the case where it is operated with a currentdensity of 50 A/cm² or more and is kept at a high temperature than inthe case where it is kept at a low temperature.

Next, the reason why the temperature increase of the external connectionterminal corresponding to the tip of the base material can be suppressedso as to keep high reliability in the connection with a mother substrateby setting the contact area between the base material and the upper orlower face of the semiconductor chip to be smaller than ½ of the upperor lower face will be described.

Conventionally, the heat resistance from a Si semiconductor device to abase material is designed so that the temperature of the semiconductordevice can be 150° C. when the temperature of the base material is 90°C., namely, a temperature difference therebetween can be 60° C., in thecase where normal rated power is given to the semiconductor device. Inother words, a current corresponding to heat generation to increase thetemperature of the Si semiconductor device to 150° C. can be allowed toflow. Similarly, in the case where a SiC (silicon carbide) power deviceis mounted, it is necessary to set the temperature of the SiCsemiconductor apparatus to 200° C. and the temperature of the basematerial to 90° C. in the same manner as in the Si semiconductor deviceunless the package is largely modified. The temperature difference inthe SiC semiconductor apparatus is 110° C., which is substantially twiceas large as that in the Si semiconductor apparatus. Accordingly, theaforementioned temperature range can be attained if the heat resistancebetween the SiC chip including the SiC semiconductor device(corresponding to the semiconductor chip 61 of this embodiment) and thebase material is set to be twice as large as that set in the Si chipincluding the Si semiconductor device. In order to realize this, whenthe contact area on the upper or lower face (front or back face) of theSiC chip is a half of the upper or lower face, the heat resistance isdoubled, which means that the SiC semiconductor device can be normallyoperated at 200° C. with the temperature of the base material kept at90° C. or less. When another radiation mechanism (base material) withhigh heat conductivity is additionally provided, the temperatureincrease of the base material can be suppressed while suppressing thetemperature increase of the SiC semiconductor device by further reducingthe contact area. In other words, when the contact area with the basematerial on the upper or lower face of the SiC chip is a half or less ofthe upper or lower face, a stable operation can be performed withoutcausing the temperature increase. At this point, when the heatresistance of the package itself is changed to 200° C. or more bylargely modifying the package resin or the like to a metal or the like,the half contact area should be further reduced.

On the contrary, when the contact area between the SiC chip and the basematerial is a half or more of the upper or lower face (front or backface) of the SiC chip, in the case where a current is allowed to flowwith the temperature of the SiC semiconductor device set to 200° C.corresponding to the heat resistant temperature of the package, thetemperature of the base material exceeds 90° C., and hence, there arisesa problem derived from the heat generation in a contact portion betweenthe base material and a print wiring board or the like.

Example 1

FIG. 6 is a cross-sectional view of a semiconductor apparatus accordingto Example 1 of Embodiment 2. As shown in FIG. 6, the semiconductorapparatus of this example includes a power transistor TR1, that is, avertical MISFET.

As shown in FIG. 6, the power transistor TR1 (a semiconductor chip 61)includes an N-type drift layer 31 (active region) occupying most of aSiC substrate made of a wide band gap semiconductor; a P-type base layer32 formed in the N-type drift layer 31 by doping it with a P-typeimpurity; an N⁺-type source layer 33 formed in the P-type base layer 32by doping it with a high concentration N-type impurity; a gateinsulating film 35 of a silicon oxide film formed in a surface portionof the SiC substrate over the P-type base layer 32, the N-type driftlayer 31 and the N⁺-type source layers 33 sandwiching the P-type baselayer 32; a gate electrode 36 of a metal such as Al or polysiliconprovided on the gate insulating film 35; a source electrode 37 formed ina surface portion of the SiC substrate over the N⁺-type source layers 33sandwiching the P-type base layer 32; an interlayer insulating film 38of a silicon oxide film provided on the SiC substrate; a gateinterconnect/plug 40 made of a metal such as Al and penetrating theinterlayer insulating film 38 to be connected to the gate electrode 36;a leading electrode 42 of the gate interconnect/plug 40; and a sourceinterconnect/plug 41 made of a metal such as Al and penetrating theinterlayer insulating film 38 to be connected to every source electrode37.

A portion of the source interconnect/plug 41 positioned on the upperface of the interlayer insulating film 38 is provided in the shape of aplate, this portion is connected to a base material 63 (lead) made of ametal such as Cu through a metal fine line 70, and the tip of the basematerial 63 works as an external connection terminal 63 a to beconnected to an output terminal portion of a mother substrate.

Also, a back electrode 39 made of a metal such as Ni or Ni silicidealloy is provided on the lower face of the N-type drift layer 31, theback electrode 39 is connected to a base material 62 (die pad) through afirst intermediate member 65, and the tip of the base material 62 worksas an external connection terminal 62 a to be connected to the ground ofthe mother substrate.

Furthermore, the leading electrode 42 is connected to a base material 64(lead) provided on a cross-section not shown through a metal fine line71, and the tip of the base material 64 works as an external connectionterminal 64 a to be connected to a gate bias supplying part of themother substrate.

Furthermore, a heat conducting member 66 made of alumina (ceramic) isprovided on the upper face of the power transistor TR1, and a radiationfin 67 made of a copper alloy plate is provided on the upper face of theheat conducting member 66.

On the upper side of the substrate 62, the power transistor TR1, thefirst intermediate member 65, the base materials 63 and 64, the metalfine lines 70 and 71 and the heat conducting member 66 are encapsulatedwith an encapsulating material 68 made of epoxy resin. A portion of theencapsulating material 68 sandwiched between the power transistor TR1and the base material 62 works as a second intermediate member 68 a.

Next, a method for fabricating the semiconductor apparatus of thisexample will be described. FIGS. 7A through 7C are cross-sectional viewsfor showing fabrication procedures for the semiconductor apparatus ofthis example.

First, in a step shown in FIG. 7A, the power transistor TR1(semiconductor chip 62) is mounted, with the first intermediate member65 sandwiched therebetween, on a lead frame 69 having a lead bended in aU-shape from a plate part thereof, and the source interconnect/plug 41(not shown) and the lead of the lead frame 69 are connected to eachother through the metal fine line 70. Also, the heat conducting member66 made of alumina is mounted on the upper face of the power transistorTR1.

Next, in a step shown in FIG. 7B, the power transistor TR1, a part ofthe lead frame 69, the first intermediate member 65 and the metal fineline 70 are encapsulated with the encapsulating material 68 made ofepoxy resin. At this point, the upper face (top face) of the heatconducting member 66 is exposed from the encapsulating material 68.

Then, in a step shown in FIG. 7C, the lead frame 69 is cut, so thatportions thereof to be used as the base material 62 including theexternal connection terminal 62 a and as the base material 63 includingthe external connection terminal 63 a can remain. Also, the radiationfin 67 made of Cu or the like is provided on the upper face of the heatconducting member 66. Through these steps, the structure of thesemiconductor apparatus shown in FIG. 6 is obtained.

Although the base material 64 present on the cross-section not shown andthe leading electrode are connected to each other through the metal fineline 71 as shown in FIG. 6, the corresponding portion is not shown inFIGS. 7A through 7C.

FIG. 8 is a cross-sectional view of exemplified mounting of the powertransistor TR1 on a print wiring board. As shown in this drawing, in theprint wiring board 80, a ground line 81, a through hole 83 having anelectrically conductive layer connected to the ground line 81, a sourcevoltage supplying line 82 and a through hole 84 having an electricallyconductive layer connected to the source voltage supplying line 82 areformed. The external connection terminal 62 a of the semiconductorapparatus is inserted into the through hole 83 to be connected to theground line 81 by soldering (not shown), and the external connectionterminal 63 a is inserted into the through hole 84 to be connected to anoutput terminal 82 by soldering (not shown).

Although the print wiring board 80 is provided with a gate biassupplying line and a corresponding through hole and the externalconnection terminal 64 a (see FIG. 6) is inserted into the through holeto be connected to the gate bias supplying line by soldering in thestate shown in FIG. 8, this is not shown in the drawing.

In the state shown in FIG. 8, most of heat generated in the powertransistor TR1 is transmitted through the heat conducting member 66 andreleased to the outside from the radiation fin 67, and therefore, it isunderstood that heat transmitted to the external connection terminals 62a and 63 a is suppressed to be small.

Example 2

FIG. 9 is a cross-sectional view of a semiconductor apparatus accordingto Example 2 of Embodiment 2. The semiconductor apparatus of thisexample includes a Schottky diode in addition to a power transistor TR1having the structure described in Example 1.

The Schottky diode D1 includes an N-type drift layer 21 (active region)occupying most of a SiC substrate made of a wide band gap semiconductorand a Schottky electrode 22 made of Ni in Schottky contact with theN-type drift layer 21. The back face of the N-type drift layer 21 of theSchottky diode D1 is connected to a source interconnect/plug 41 of thepower transistor TR1. Also, the Schottky electrode 22 is connected to abase material 63 made of a metal such as Cu through a first intermediatemember 74 made of a metal such as Cu, and the tip of the base material63 works as an external connection terminal 63 a to be connected to anoutput terminal portion of a mother substrate. In this example, aportion of an encapsulating material 68 sandwiched between the Schottkyelectrode 22 of the Schottky diode D1 and the base material 63corresponds to a second intermediate member 68 b.

Also, the semiconductor apparatus includes a base material 62 (die pad)that is connected to a back electrode 39 of the power transistor TR1through the first intermediate member 65 and whose tip works as anexternal connection terminal 62 a to be connected to the ground of themother substrate; and a base material 64 (lead) that is connected to aleading electrode 42 of the power transistor TR1 through a metal fineline 71 and whose tip works as an external connection terminal 64 a. Aportion of the encapsulating material 68 sandwiched between the powertransistor TR1 and the base material 62 corresponds to a secondintermediate member 68 a in the same manner as in Example 1.

Also in this example, the fabrication procedures are the same as thoseof Example 1, and a state where the semiconductor apparatus is mountedon a mother substrate (print wiring board) is the same as that shown inFIG. 8. Accordingly, in this example, while attaining high densitypackaging by containing the power transistor TR1 and the Schottky diodeD1 in one package, heat transmitted to the external connection terminals62 a and 63 a can be suppressed to be small, and hence, reliability inconnection to the mother substrate can be kept high.

Instead of employing the structure shown in FIG. 9, the Schottky diodeD1 may be disposed between a heat conducting member 66 and the sourceinterconnect/plug 41 of the power transistor TR1. In this case, theSchottky electrode 22 may be connected to the base material 63 through ametal fine line.

Example 3

FIG. 10 is a cross-sectional view of a semiconductor apparatus accordingto Example 3 of Embodiment 2. As shown in FIG. 10, the semiconductorapparatus of this example includes a power transistor TR1, that is, avertical MISFET, having the same structure as those of Examples 1 and 2.As a characteristic of this example, the semiconductor apparatus is notencapsulated with a resin but has a glass encapsulation structure usinga metal cap.

The semiconductor apparatus of this example includes, as shown in FIG.10, a base 81 made of an insulator such as ceramic; base materials 62and 63 and a supporting member 83 that are patterned from a metal plateof Cu or the like formed on the base 81 and work as base materials; apower transistor TR1 (semiconductor chip 61) mounted on the basematerial 62 and the supporting member 83; and a heat conducting member66 provided on the upper face of the power transistor TR1. The base 81is provided with through holes 88 and 89 corresponding to externalconnection terminals and electrically conductive films 84 and 86 formedover the inner walls of the through holes 88 and 89 to extend to theupper and lower faces of the base 81 (or electrically conductive rodspenetrating through the through holes 88 and 89). Also, externalconnection terminals 85 and 87 to be connected to a mother substrate(print wiring board) are provided on the electrically conductive films84 and 86 on the back face of the base 81.

The end of a back electrode (not shown) of the power transistor TR1 isdirectly connected to the base material 62, and the base material 62 isconnected to the external connection terminal 85 through theelectrically conductive film 84 (or the electrically conductive rodpenetrating through the through hole 88). Also, a sourceinterconnect/plug (not shown) of the power transistor TR1 is connectedto the base material 63 through a metal fine line 70, and the basematerial 63 is connected to the external connection terminal 87 throughthe electrically conductive film 86 (or the electrically conductive rodpenetrating through the through hole 89).

Although not shown in the drawing, a leading electrode is connected to abase material through a metal fine line on a cross-section not shown,and the base material is connected to an external connection terminalthrough an electrically conductive film formed within a through hole ofthe base 81 to extend to the upper and lower faces of the base 81.

The power transistor TR1, the base material 62, the base material 63,the metal fine line 70, the supporting member 83 and the heat conductingmember 66 are encapsulated, together with an encapsulating material 68of glass, within a metal cap 82 made of a metal such as copper alloy.The base 81 and the metal cap 82 together form a vessel forencapsulating the semiconductor chip 61 (power transistor TR1), the basematerials 62 and 63 and the heat conducting member 66.

It is noted that the encapsulating material 68 may be an inert gas, theair or a gas reduced in the pressure to a very low pressure (what iscalled a vacuum atmosphere gas).

The upper face of the heat conducting member 66 is in contact with theinner wall of the metal cap 82, and a radiation fin 67 made of a copperalloy plate or the like is provided on the outer wall of the metal cap82 in a position corresponding to the portion of the inner wall incontact with the heat conducting member 66.

In this example, the base material 62 and the metal fine line 70 are incontact with merely a part of the back face of the power transistor TR1,and the glass with comparatively low heat conductivity occupies most ofa region sandwiched between the base 81 and the power transistor TR1.Therefore, heat generated from the power transistor TR1 is minimallytransmitted to the base 81 and the base materials 62 and 63 but most ofthe heat is released through the heat conducting member 66 and the wallsof the metal cap 82 from the radiation fin 67. Accordingly, reliabilityin connection between the external connection terminal and a mothersubstrate can be improved.

INDUSTRIAL APPLICABILITY

The present invention can be utilized as a semiconductor apparatus or asemiconductor power module including a semiconductor device, such as aMISFET, a MESFET, a Schottky diode, a pn diode, a J-FET or a thyrister,using a wide band gap semiconductor such as silicon carbide (SiC), anitride of a group III element such like GaN or AlN, or diamond.

1. A semiconductor apparatus comprising: a semiconductor chip includinga power semiconductor device constructed by using a wide band gapsemiconductor, the semiconductor chip having an upper surface and alower surface opposite to the upper surface; a first base material madeof an electrically conductive material and electrically connected to apart of the lower surface of said semiconductor chip; a heat conductingmember coming in contact with a part of the upper surface of saidsemiconductor chip opposite to the lower surface and releasing heatdirectly from said semiconductor chip; and an encapsulating material forencapsulating said semiconductor chip and said heat conducting member,wherein the semiconductor apparatus further comprises a second basematerial made of a metal material and disposed on a part of said uppersurface of said semiconductor chip, wherein said power semiconductordevice is a vertical element, wherein a part of said first base materialis extruded outside said encapsulating material and works as a firstexternal connection terminal, wherein a part of said second basematerial is extruded outside said encapsulating material and works as asecond external connection terminal, wherein a first intermediate membermade of an electrically conductive material and a second intermediatemember made of a material having lower heat conductivity than said firstintermediate member are provided under the lower surface of saidsemiconductor chip and between said first base material and saidsemiconductor chip, wherein the first intermediate member and the secondintermediate member touch the lower surface of the semiconductor chipand the first base material, and an area where the second intermediatemember touches the lower surface of the semiconductor chip is largerthan an area where the first intermediate member touches the lowersurface of the semiconductor chip, and wherein the semiconductor chipand the first base material are electrically connected with each otherthrough the first intermediate member, and wherein an ohmic electrode isdisposed on an entire surface of the lower surface of the semiconductorchip.
 2. The semiconductor apparatus of claim 1, wherein said powersemiconductor device has a region where a current passes at a currentdensity of 50 A/cm² or more.
 3. The semiconductor apparatus of claim 1or 2, wherein said encapsulating material is made of a resin or glass,and said heat conducting member is exposed from said encapsulatingmaterial.
 4. The semiconductor apparatus of claim 3, further comprisinga radiation fin that is in contact with said heat conducting member andis extruded outside said encapsulating material.
 5. The semiconductorapparatus of claim 1 or 2, further comprising a film for covering saidencapsulating material.
 6. The semiconductor apparatus of claim 5,further comprising a radiation fin opposing said heat conducting memberwith said film sandwiched therebetween.
 7. The semiconductor apparatusof claim 1, further comprising another semiconductor chip that isstacked on said semiconductor chip.
 8. The semiconductor apparatus ofclaim 1, wherein said first external connection terminal of said firstbase material is configured to be mounted on a print wiring board. 9.The semiconductor apparatus of claim 1, wherein said wide band gapsemiconductor is SiC.
 10. The semiconductor apparatus of claim 1,wherein the ohmic electrode comprises nickel.